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  <div class="edit"><a href="https://gem5.googlesource.com/public/gem5-website/+/refs/heads/master/README.md">Edit this page</a></div>
  <b>authors:</b> Jason Lowe-Power<br>
  

  <br>
  <h1 id="moesi-cmp-directory">MOESI CMP Directory</h1>

<h3 id="protocol-overview">Protocol Overview</h3>

<ul>
  <li>TODO: cache hierarchy</li>
</ul>

<!-- end list -->

<ul>
  <li>In contrast with the MESI protocol, the MOESI protocol introduces an
additional <strong>Owned</strong> state.</li>
  <li>The MOESI protocol also includes many coalescing optimizations not
available in the MESI protocol.</li>
</ul>

<h3 id="related-files">Related Files</h3>

<ul>
  <li><strong>src/mem/protocols</strong>
    <ul>
      <li><strong>MOESI_CMP_directory-L1cache.sm</strong>: L1 cache controller
specification</li>
      <li><strong>MOESI_CMP_directory-L2cache.sm</strong>: L2 cache controller
specification</li>
      <li><strong>MOESI_CMP_directory-dir.sm</strong>: directory controller
specification</li>
      <li><strong>MOESI_CMP_directory-dma.sm</strong>: dma controller specification</li>
      <li><strong>MOESI_CMP_directory-msg.sm</strong>: message type specification</li>
      <li><strong>MOESI_CMP_directory.slicc</strong>: container file</li>
    </ul>
  </li>
</ul>

<h3 id="l1-cache-controller">L1 Cache Controller</h3>

<h4 id="stable-states-and-invariants"><strong>Stable States and Invariants</strong></h4>

<table>
  <thead>
    <tr>
      <th>States</th>
      <th>Invariants</th>
    </tr>
  </thead>
  <tbody>
    <tr>
      <td><strong>MM</strong></td>
      <td>The cache block is held exclusively by this node and is potentially modified (similar to conventional “M” state).</td>
    </tr>
    <tr>
      <td><strong>MM_W</strong></td>
      <td>The cache block is held exclusively by this node and is potentially modified (similar to conventional “M” state). Replacements and DMA accesses are not allowed in this state. The block automatically transitions to MM state after a timeout.</td>
    </tr>
    <tr>
      <td><strong>O</strong></td>
      <td>The cache block is owned by this node. It has not been modified by this node. No other node holds this block in exclusive mode, but sharers potentially exist.</td>
    </tr>
    <tr>
      <td><strong>M</strong></td>
      <td>The cache block is held in exclusive mode, but not written to (similar to conventional “E” state). No other node holds a copy of this block. Stores are not allowed in this state.</td>
    </tr>
    <tr>
      <td><strong>M_W</strong></td>
      <td>The cache block is held in exclusive mode, but not written to (similar to conventional “E” state). No other node holds a copy of this block. Only loads and stores are allowed. Silent upgrade happens to MM_W state on store. Replacements and DMA accesses are not allowed in this state. The block automatically transitions to M state after a timeout.</td>
    </tr>
    <tr>
      <td><strong>S</strong></td>
      <td>The cache block is held in shared state by 1 or more nodes. Stores are not allowed in this state.</td>
    </tr>
    <tr>
      <td><strong>I</strong></td>
      <td>The cache block is invalid.</td>
    </tr>
  </tbody>
</table>

<h4 id="fsm-abstraction"><strong>FSM Abstraction</strong></h4>

<p><strong>The notation used in the controller FSM diagrams is described
<a href="#Coherence_controller_FSM_Diagrams" title="wikilink">here</a>.</strong></p>

<p><img src="/assets/img/MOESI_CMP_directory_L1cache_FSM.jpg" alt="MOESI_CMP_directory_L1cache_FSM.jpg" title="MOESI_CMP_directory_L1cache_FSM.jpg" /></p>

<h4 id="optimizations"><strong>Optimizations</strong></h4>

<table>
  <thead>
    <tr>
      <th>States</th>
      <th>Description</th>
    </tr>
  </thead>
  <tbody>
    <tr>
      <td><strong>SM</strong></td>
      <td>A GETX has been issued to get exclusive permissions for an impending store to the cache block, but an old copy of the block is still present. Stores and Replacements are not allowed in this state.</td>
    </tr>
    <tr>
      <td><strong>OM</strong></td>
      <td>A GETX has been issued to get exclusive permissions for an impending store to the cache block, the data has been received, but all expected acknowledgments have not yet arrived. Stores and Replacements are not allowed in this state.</td>
    </tr>
  </tbody>
</table>

<p><strong>The notation used in the controller FSM diagrams is described
<a href="#Coherence_controller_FSM_Diagrams" title="wikilink">here</a>.</strong></p>

<p><img src="/assets/img/MOESI_CMP_directory_L1cache_optim_FSM.jpg" alt="MOESI_CMP_directory_L1cache_optim_FSM.jpg" title="MOESI_CMP_directory_L1cache_optim_FSM.jpg" /></p>

<h3 id="l2-cache-controller">L2 Cache Controller</h3>

<h4 id="stable-states-and-invariants-1"><strong>Stable States and Invariants</strong></h4>

<table>
  <thead>
    <tr>
      <th>Intra-chip Inclusion</th>
      <th>Inter-chip Exclusion</th>
      <th>States</th>
      <th>Description</th>
    </tr>
  </thead>
  <tbody>
    <tr>
      <td><strong><span style="color:#808080">Not in any L1 or L2 at this chip</span></strong></td>
      <td><strong>May be present at other chips</strong></td>
      <td><strong>NP/I</strong></td>
      <td>The cache block at this chip is invalid.</td>
    </tr>
    <tr>
      <td><strong><span style="color:#00CC99">Not in L2, but in 1 or more L1s at this chip</span></strong></td>
      <td><strong>May be present at other chips</strong></td>
      <td><strong>ILS</strong></td>
      <td>The cache block is not present at L2 on this chip. It is shared locally by L1 nodes in this chip.</td>
    </tr>
    <tr>
      <td><strong>ILO</strong></td>
      <td>The cache block is not present at L2 on this chip. Some L1 node in this chip is an owner of this cache block.</td>
      <td> </td>
      <td> </td>
    </tr>
    <tr>
      <td><strong>ILOS</strong></td>
      <td>The cache block is not present at L2 on this chip. Some L1 node in this chip is an owner of this cache block. There are also L1 sharers of this cache block in this chip.</td>
      <td> </td>
      <td> </td>
    </tr>
    <tr>
      <td><strong>Not present at any other chip</strong></td>
      <td><strong>ILX</strong></td>
      <td>The cache block is not present at L2 on this chip. It is held in exclusive mode by some L1 node in this chip.</td>
      <td> </td>
    </tr>
    <tr>
      <td><strong>ILOX</strong></td>
      <td>The cache block is not present at L2 on this chip. It is held exclusively by this chip and some L1 node in this chip is an owner of the block.</td>
      <td> </td>
      <td> </td>
    </tr>
    <tr>
      <td><strong>ILOSX</strong></td>
      <td>The cache block is not present at L2 on this chip. It is held exclusively by this chip. Some L1 node in this chip is an owner of the block. There are also L1 sharers of this cache block in this chip.</td>
      <td> </td>
      <td> </td>
    </tr>
    <tr>
      <td><strong><span style="color:#99CCFF">In L2, but not in any L1 at this chip</span></strong></td>
      <td><strong>May be present at other chips</strong></td>
      <td><strong>S</strong></td>
      <td>The cache block is not present at L1 on this chip. It is held in shared mode at L2 on this chip and is also potentially shared across chips.</td>
    </tr>
    <tr>
      <td><strong>O</strong></td>
      <td>The cache block is not present at L1 on this chip. It is held in owned mode at L2 on this chip. It is also potentially shared across chips.</td>
      <td> </td>
      <td> </td>
    </tr>
    <tr>
      <td><strong>Not present at any other chip</strong></td>
      <td><strong>M</strong></td>
      <td>The cache block is not present at L1 on this chip. It is present at L2 on this chip and is potentially modified.</td>
      <td> </td>
    </tr>
    <tr>
      <td><strong><span style="color:#CC99FF">Both in L2, and 1 or more L1s at this chip</span></strong></td>
      <td><strong>May be present at other chips</strong></td>
      <td><strong>SLS</strong></td>
      <td>The cache block is present at L2 in shared mode on this chip. There exists local L1 sharers of the block on this chip. It is also potentially shared across chips.</td>
    </tr>
    <tr>
      <td><strong>OLS</strong></td>
      <td>The cache block is present at L2 in owned mode on this chip. There exists local L1 sharers of the block on this chip. It is also potentially shared across chips.</td>
      <td> </td>
      <td> </td>
    </tr>
    <tr>
      <td><strong>Not present at any other chip</strong></td>
      <td><strong>OLSX</strong></td>
      <td>The cache block is present at L2 in owned mode on this chip. There exists local L1 sharers of the block on this chip. It is held exclusively by this chip.</td>
      <td> </td>
    </tr>
  </tbody>
</table>

<h4 id="fsm-abstraction-1"><strong>FSM Abstraction</strong></h4>

<p>The controller is described in 2 parts. The first picture shows
transitions between all “intra-chip inclusion” categories and within
categories 1, 3, 4. Transitions within category 2 (Not in L2, but in 1
or more L1s at this chip) are shown in the second picture.</p>

<p><strong>The notation used in the controller FSM diagrams is described
<a href="#Coherence_controller_FSM_Diagrams" title="wikilink">here</a>. Transitions
involving other chips are annotated in
<span style="color:#CC3300">brown</span>.</strong></p>

<p><img src="/assets/img/MOESI_CMP_directory_L2cache_FSM_part_1.jpg" alt="MOESI_CMP_directory_L2cache_FSM_part_1.jpg" title="MOESI_CMP_directory_L2cache_FSM_part_1.jpg" /></p>

<p>The second picture below expands the central hexagonal portion of the
above picture to show transitions within category 2 (Not in L2, but in 1
or more L1s at this chip).</p>

<p><strong>The notation used in the controller FSM diagrams is described
<a href="#Coherence_controller_FSM_Diagrams" title="wikilink">here</a>. Transitions
involving other chips are annotated in
<span style="color:#CC3300">brown</span>.</strong></p>

<p><img src="/assets/img/MOESI_CMP_directory_L2cache_FSM_part_2.jpg" alt="MOESI_CMP_directory_L2cache_FSM_part_2.jpg" title="MOESI_CMP_directory_L2cache_FSM_part_2.jpg" /></p>

<h3 id="directory-controller">Directory Controller</h3>

<h4 id="stable-states-and">**Stable States and</h4>
<p>Invariants**</p>

<table>
  <thead>
    <tr>
      <th>States</th>
      <th>Invariants</th>
    </tr>
  </thead>
  <tbody>
    <tr>
      <td><strong>M</strong></td>
      <td>The cache block is held in exclusive state by only 1 node (which is also the owner). There are no sharers of this block. The data is potentially different from that in memory.</td>
    </tr>
    <tr>
      <td><strong>O</strong></td>
      <td>The cache block is owned by exactly 1 node. There may be sharers of this block. The data is potentially different from that in memory.</td>
    </tr>
    <tr>
      <td><strong>S</strong></td>
      <td>The cache block is held in shared state by 1 or more nodes. No node has ownership of the block. The data is consistent with that in memory (Check).</td>
    </tr>
    <tr>
      <td><strong>I</strong></td>
      <td>The cache block is invalid.</td>
    </tr>
  </tbody>
</table>

<h4 id="fsm-abstraction-2"><strong>FSM Abstraction</strong></h4>

<p><strong>The notation used in the controller FSM diagrams is described
<a href="#Coherence_controller_FSM_Diagrams" title="wikilink">here</a>.</strong></p>

<p><img src="/assets/img/MOESI_CMP_directory_dir_FSM.jpg" alt="MOESI_CMP_directory_dir_FSM.jpg" title="MOESI_CMP_directory_dir_FSM.jpg" /></p>

<h3 id="other-features">Other features</h3>

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